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Rev 0; 4/06
Real-Time Clocks
General Description
The DS17285, DS17485, DS17885, DS17287, DS17487, and DS17887 real-time clocks (RTCs) are designed to be successors to the industry-standard DS12885 and DS12887. The DS17285, DS17485, and DS17885 (hereafter referred to as the DS17x85) provide a real-time clock/calendar, one time-of-day alarm, three maskable interrupts with a common interrupt output, a programmable square wave, and 114 bytes of battery-backed NV SRAM. The DS17x85 also incorporates a number of enhanced functions including a silicon serial number, power-on/off control circuitry, and 2k, 4k, or 8kbytes of battery-backed NV SRAM. The DS17287, DS17487, and DS17887 (hereafter referred to as the DS17x87) integrate a quartz crystal and lithium energy source into a 24-pin encapsulated DIP package. The DS17x85 and DS17x87 power-control circuitry allows the system to be powered on by an external stimulus such as a keyboard or by a time-and-date (wake-up) alarm. The PWR output pin is triggered by one or either of these events, and is used to turn on an external power supply. The PWR pin is under software control, so that when a task is complete, the system power can then be shut down. For all devices, the date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. It also operates in either 24-hour or 12-hour format with an AM/PM indicator. A precision temperature-compensated circuit monitors the status of VCC. If a primary power failure is detected, the device automatically switches to a backup supply. A lithium coin cell battery can be connected to the VBAT input pin on the DS17x85 to maintain time and date operation when primary power is absent. The DS17x85 and DS17x87 include a VBAUX input used to power auxiliary functions such as PWR control. The device is accessed through a multiplexed byte-wide interface.
Features
Incorporates Industry-Standard DS12887 PC Clock Plus Enhanced Functions RTC Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap Year Compensation Through 2099 Optional +3.0V or +5.0V Operation SMI Recovery Stack 64-Bit Silicon Serial Number Power-Control Circuitry Supports System PowerOn from Date/Time Alarm or Key Closure Crystal Select Bit Allows Operation with 6pF or 12.5pF Crystal 12-Hour or 24-Hour Clock with AM and PM in 12-Hour Mode 114 Bytes of General-Purpose, Battery-Backed NV SRAM Extended Battery-Backed NV SRAM 2048 Bytes (DS17285/DS17287) 4096 Bytes (DS17485/DS17487) 8192 Bytes (DS17885/DS17887) RAM Clear Function Interrupt Output with Six Independently Maskable Interrupt Flags Time-of-Day Alarm Once per Second to Once per Day End of Clock Update Cycle Flag Programmable Square-Wave Output Automatic Power-Fail Detect and Switch Circuitry Available in PDIP, SO, or TSOP Package (DS17285, DS17485, DS17885) Optional Encapsulated DIP (EDIP) Package with Integrated Crystal and Battery (DS17287, DS17487, DS17887) Optional Industrial Temperature Range Available Underwriters Laboratory (UL) Recognized
Ordering Information, Pin Configurations, and Typical Operating Circuit appear at end of data sheet.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Applications
Embedded Systems Utility Meters Security Systems Network Hubs, Bridges, and Routers
______________________________________________ Maxim Integrated Products
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Pin Relative to Ground ....-0.3V to +6.0V Operating Temperature Range (Noncondensing) Commercial.........................................................0C to +70C Industrial ..........................................................-40C to +85C Storage Temperature.........................................-55C to +125C Soldering Temperature .....................See IPC/JEDEC J-STD-020 Specification (Note 1) Soldering Temperature (leads, 10 seconds) ...................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to +5.5V, or VCC = +2.7V to +3.7V, TA = Over the operating temperature range, unless otherwise noted. Typical values are with TA = +25C, VCC = 5.0V or 3.0V and VBAT = 3.0V, unless otherwise noted.) (Note 2)
PARAMETER Supply Voltage (Note 3) VBAT Input Voltage VBAUX Input Voltage (Note 3) SYMBOL VCC VBAT VBAUX (-5) (-3) (Note 3) (-5) (-3) (-5) Input Logic 1 (Note 3) VIH (-3) Input Logic 0 (Note 3) VCC Power-Supply Current (Note 4) VCC Standby Current (Notes 4, 5) Input Leakage I/O Leakage Output Logic 1 Voltage (Note 3) Output Logic 0 Voltage AD0-AD7, IRQ, SQW (Note 3) Output Logic 0 Voltage PWR (Note 3) Power-Fail Voltage (Note 3) VRT Trip Point VIL ICC1 ICCS IIL IOL VOH VOL VOL VPF VRTTRIP (Note 6) (-5), -1.0mA (-3), -0.4mA (-5), +2.1mA (-3), +0.8mA (-5), +10mA (-3), +4mA (-5) (-3) (Note 3) 4.25 2.5 4.37 2.6 1.3 (-5) (-3) (-5) (-3) (-5) (-3) -1.0 -1.0 2.4 2.4 0.4 0.4 0.4 0.4 4.5 2.7 2.0 -0.3 -0.3 25 15 1.0 0.5 2.2 CONDITIONS MIN 4.5 2.7 2.5 2.5 TYP 5.0 3.0 3.0 3.0 MAX 5.5 3.7 3.7 5.2 3.7 VCC + 0.3 V VCC + 0.3 +0.8 +0.6 50 30 3.0 2.0 +1.0 +1.0 V mA mA A A V V V V V UNITS V V V
2
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Real-Time Clocks
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBAT = 3.0V, TA = Over the operating range, unless otherwise noted.) (Note 1)
PARAMETER VBAT or VBAUX Current (Oscillator On); TA = +25C, VBAT = 3.0V VBAT or VBAUX Current (Oscillator Off) SYMBOL IBAT IBATDR (Note 7) (Note 7) CONDITIONS MIN TYP 500 50 MAX 700 400 UNITS nA nA
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
AC ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to +5.5V, TA = Over the operating range, unless otherwise noted.) (Note 2)
PARAMETER Cycle Time Pulse Width, RD or WR Low Pulse Width, RD or WR High Input Rise and Fall Chip-Select Setup Time Before RD or WR Chip-Select Hold Time Read-Data Hold Time Write-Data Hold Time Address Setup Time to ALE Fall Address Hold Time to ALE Fall RD or WR High Setup to ALE Rise Pulse Width ALE High Delay Time ALE Low to RD Low Output Data Delay Time from RD Data Setup Time IRQ Release from RD SYMBOL tCYC PWRWL PWRWH tR, tF tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW tIRD (Note 8) 20 0 10 0 20 10 25 40 30 20 30 2 120 50 CONDITIONS MIN 240 120 80 30 TYP MAX DC UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +3.7V, TA = Over the operating range, unless otherwise noted.) (Note 2)
PARAMETER Cycle Time Pulse Width, RD or WR Low Pulse Width, RD or WR High Input Rise and Fall Chip-Select Setup Time Before RD or WR Chip-Select Hold Time Read-Data Hold Time Write-Data Hold Time Address Setup Time to ALE Fall Address Hold Time to ALE Fall RD or WR High Setup to ALE Rise Pulse Width ALE High Delay Time ALE Low to RD Low Output Data Delay Time from RD Data Setup Time IRQ Release from RD SYMBOL tCYC PWRWL PWRWH tR, tF tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW tIRD (Note 8) 20 0 10 0 40 10 30 40 30 20 70 2 200 90 CONDITIONS MIN 360 200 150 30 TYP MAX DC UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
Write Timing
tCYC AS tASD RD tASD WR PWRWH tCS CS tASL AD0-AD7 WRITE tAHL tDSW tDHW tASED PWRWL tCH PWASH
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Read Timing
tCYC
ALE
PWASH
tASD
tASED PWRWH PWRWL
RD tASD WR
tCH tCS CS
tASL
tAHL
tDDR
tDHR
AD0-AD7 tIRD IRQ
Power-Up/Power-Down Timing
VCC VPF(MAX)
VPF(MIN)
tF
tR tREC
CS, WR, RD
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH IMPEDANCE AD0-AD7 VALID VALID
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40C to +85C) (Note 2)
PARAMETER Recovery at Power-Up VCC Fall Time, VPF(MAX) to VPF(MIN) VCC Fall Time, VPF(MAX) to VPF(MIN) SYMBOL tREC tF tR (Note 9) CONDITIONS MIN 20 300 0 TYP MAX 150 UNITS ms s s
DATA RETENTION (DS17x87 ONLY)
(TA = +25C)
PARAMETER Expected Data Retention SYMBOL tDR (Note 9) CONDITIONS MIN 10 TYP MAX UNITS Years
CAPACITANCE
(TA = +25C) (Note 10)
PARAMETER Capacitance on All Input Pins Except X1 Capacitance on IRQ, SQW, and DQ0-DQ7 Pins SYMBOL CIN CIO (Note 10) (Note 10) CONDITIONS MIN TYP MAX 12 12 UNITS pF pF
AC TEST CONDITIONS
PARAMETER Input Pulse Levels: Output Load Including Scope and Jig: Input and Output Timing Measurement Reference Levels: Input Pulse Rise and Fall Times: 0 to 3.0V 50pF + 1TTL Gate Input/Output: VIL max and VIH min 5ns CONDITIONS
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode can cause loss of data.
RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85C. However, post-solder cleaning with waterwashing techniques is acceptable, provided that ultrasonic vibrations not used to prevent damage to the crystal. Note 2: Limits at -40C are guaranteed by design and not production tested. Note 3: All voltages are referenced to ground. Note 4: All outputs are open. Note 5: Specified with CS = RD = WR = VCC, ALE, AD0-AD7 = 0. Note 6: Applies to the AD0-AD7 pins, IRQ, and SQW when each is in a high-impedance state. Note 7: Measured with a 32.768kHz crystal attached to X1 and X2. Note 8: Measured with a 50pF capacitance load plus 1TTL gate. Note 9: If the oscillator is disabled in software, or if the countdown chain is in reset, tREC is bypassed, and the part becomes immediately accessible. Note 10: Guaranteed by design. Not production tested. 6 _____________________________________________________________________ Note 1:
Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. INPUT VOLTAGE
DS17285/87 toc01
SUPPLY CURRENT vs. TEMPERATURE
VBAT = 3.0V SUPPLY CURRENT (nA)
DS17285/87 toc02
OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
DS17285/87 toc03
400 VCC = 0V 350
400
32768.7 32768.6 OSCILLATOR FREQUENCY (Hz) 32768.5 32768.4 32768.3 32768.2 32768.1
SUPPLY CURRENT (nA)
350
300
300
250
200 2.5 2.8 3.0 3.3 3.5 3.8 VBAT (V)
250 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
32768.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
Pin Description
PIN 24 28 NAME FUNCTION Active-Low Power-On Reset. This open-drain output pin is intended for use as an on/off control for the system power. With VCC voltage removed from the device, PWR can be automatically activated from a kickstart input by the KS pin or from a wake-up interrupt. Once the system is powered on, the state of PWR can be controlled by bits in the control registers. The PWR pin can be connected through a pullup resistor to a positive supply. For 5V operation, the voltage of the pullup supply should be no greater than 5.7V. For 3V operation, the voltage on the pullup supply should be no greater than 3.9V. Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF or 12.5pF. Pin X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, pin X2, is floated if an external oscillator is connected to pin X1. These pins are missing (N.C.) on the EDIP package.
1
8
PWR
2, 3
9, 10
X1, X2
4-11
12-17, 19, 20
Multiplexed Bidirectional Address/Data Bus. The addresses are presented during the first portion of the bus cycle and latched into the device by the falling edge of ALE. Write data is AD0-AD7 latched by the rising edge of WR. In a read cycle, the device outputs data during the latter portion of the RD low. The read cycle is terminated and the bus returns to a high-impedance state as RD transitions high. GND Ground
12, 16
21, 22, 26
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Pin Description (continued)
PIN 24 13 28 23 NAME FUNCTION Active-Low Chip-Select Input. This pin must be asserted low during a bus cycle for the device to be accessed. CS must be kept in the active state during RD and WR. Bus cycles that take place without asserting CS latch addresses, but no access occurs. Address Latch Enable Input, Active High. This input pin is used to demultiplex the address/data bus. The falling edge of ALE causes the address to be latched within the device. Active-Low Write Input. This pin defines the period during which data is written to the addressed register. Active-Low Read Input. This pin identifies the period when the device drives the bus with read data. It is an enable signal for the output buffers of the device. Active-Low Kickstart Input. When VCC is removed from the device, the system can be powered on in response to an active-low transition on the KS pin, as might be generated from a key closure. VBAUX must be present and auxiliary-battery-enable bit (ABE) must be set to 1 if the kickstart function is used, and the KS pin must be pulled up to the VBAUX supply. While VCC is applied, the KS pin can be used as an interrupt input. If not used, KS must be grounded and ABE set to 0. Active-Low Interrupt Request. This pin is an active-low output that can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin, the application software must clear all enabled flag bits contributing to the pin's active state. When no interrupt conditions are present, the IRQ level is in the high-impedance state. Multiple interrupting devices can be connected to an IRQ bus, provided that they are all open drain. The IRQ pin requires an external pullup resistor to VCC. Connection for Primary Battery. This supply input is used to power the normal clock functions when VCC is absent. Diodes placed in series between VBAT and the battery can prevent proper operation. If VBAT is not required, the pin must be grounded. UL recognized to ensure against reverse charging current when used with a lithium battery (www.maximic.com/qa/info/ul). This pin is missing (N.C.) on the EDIP package.
CS
14 15 17
24 25 27
ALE WR RD
18
28
KS
19
1
IRQ
20
2
VBAT
8
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Real-Time Clocks
Pin Description (continued)
PIN 24 28 NAME FUNCTION Active-Low RAM Clear Input. This pin is used to clear (set to logic 1) all the 114 bytes of general-purpose RAM but does not affect the RAM associated with the real time clock or extended RAM. RCLR may be invoked while the part is powered from any supply. The RCLR function is designed to be used via a human interface (shorting to ground manually or by a switch) and not to be driven with external buffers. This pin is internally pulled up. Do not use an external pullup resistor on this pin. Auxiliary Battery Input. Required for kickstart and wake-up functions. This input also supports clock/calendar and user RAM if VBAT is at lower voltage or is not used. A standard +3V lithium cell or other energy source can be used. Diodes placed in series between VBAUX and the battery may prevent proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery (www.maxim-ic.com/qa/info/ul/). For 3V VCC operation, VBAUX must be held between +2.5V and +3.7V. For 5V VCC operation, VBAUX must be held between +2.5V and +5.2V. If VBAUX is not used it should be grounded and the auxiliary-battery-enable bit bank 1, register 4BH, should = 0. Square-Wave Output. When VCC rises above VPF, bits DV1 and E32k are set to 1. This condition enables a 32kHz square-wave output. A square wave is output if either SQWE = 1 or E32k = 1. If E32k = 1, then 32kHz is output regardless of the other control bits. If E32k = 0, then the output frequency is dependent on the control bits in Register A. The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the RTC. The frequency of the SQW pin can be changed by programming Register A, as shown in Table 3. The SQW signal can be turned on and off using the SQWE bit in Register B or the E32k bit in extended register 4Bh. A 32kHz square wave is also available when VCC is less than VPF if E32k = 1, ABE = 1, and voltage is applied to the VBAUX pin. When disabled, SQW is high impedance when VCC is below VPF. DC Power Pin for Primary Power Supply. When VCC is applied within normal limits, the device is fully accessible and data can be written and read. When VCC is below VPF reads and writes are inhibited.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
21
3
RCLR
22
4
VBAUX
23
5
SQW
24
6, 7
VCC
2, 3, 16, 20 (DS17x87 only)
11, 18
N.C.
No Connection
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
X1 OSCILLATOR X2 DIVIDE BY 8 DIVIDE BY 64 DIVIDE BY 64
DS17x87 ONLY VBAT
16:1 MUX
SQUAREWAVE GENERATOR POWER CONTROL IRQ GENERATOR
SQW
GND VCC VBAUX IRQ
PWR KS
REGISTERS A, B, C, D CLOCK/CALENDAR UPDATE LOGIC CS WR RD ALE AD0-AD7 BUS INTERFACE
CLOCK/CALENDAR AND ALARM REGISTERS BUFFERED CLOCK/ CALENDAR AND ALARM REGISTERS USER RAM 114 BYTES RAM CLEAR LOGIC RLCR
SELECT
EXTENDED USER RAM 2k/4k/8k BYTES
EXTENDED RAM ADDR/ DATA REGISTERS EXTENDED CONTROL/ STATUS REGISTERS 64-BIT SERIAL NUMBER CENTURY COUNTER DATE ALARM RTC ADDRESS-2 RTC ADDRESS-3
DS17x85/87
Figure 1. Functional Diagram
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Real-Time Clocks
Detailed Description
The DS17x85 is a successor to the DS1285 real-time clock (RTC). The device provides 18 bytes of real-time clock/calendar, alarm, and control/status registers and 114 bytes of nonvolatile battery-backed RAM. The device also provides additional extended RAM in either 2k/4k/8kbytes (DS17285/DS17485/DS17885). A timeof-day alarm, six maskable interrupts with a common interrupt output, and a programmable square-wave output are available. It also operates in either 24-hour or 12-hour format with an AM/PM indicator. A precision temperature-compensated circuit monitors the status of VCC. If a primary power-supply failure is detected, the device automatically switches to a backup supply. The backup supply input supports a primary battery, such as a lithium coin cell. The device is accessed by a multiplexed address/data bus.
Table 1. Crystal Specifications* (DS17x85 Only)
PARAMETER Nominal Series Resistance Load Capacitance SYMBOL fO ESR CL 6 or 12.5 MIN TYP 32.768 50 MAX UNITS kHz k pF
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
Oscillator Circuit
The DS17x85 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal, and Figure 2 shows a functional schematic of the oscillator circuit. The oscillator is controlled by an enable bit in the control register. Oscillator startup times are highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within one second. An external 32.768kHz oscillator can also drive the DS17x85. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
COUNTDOWN CHAIN
CL1
C L2
RTC REGISTERS
DS17285/87 DS17485/87 DS17885/87
X1 CRYSTAL X2
Figure 2. Oscillator Circuit Showing Internal Bias Network
Clock Accuracy
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Figure 3 shows a typical PC board layout for isolation of the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.
LOCAL GROUND PLANE (TOP LAYER)
X1 CRYSTAL X2
Clock Accuracy (DS17287, DS17487, and DS17887)
The encapsulated DIP (EDIP) modules are trimmed at the factory to 1 minute per month accuracy at 25C.
NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED AREA (UPPER LEFT QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE DEVICE PACKAGE.
GND
Figure 3. Layout Example 11
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Power-Down/Power-Up Considerations
The RTC function continues to operate, and all the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the VCC input. VBAT or VBAUX must remain within the minimum and maximum limits when VCC is not applied. When V CC falls below VPF, the device inhibits all access, putting the part into a low-power mode. When VCC is applied and exceeds V PF (power-fail trip point), the device becomes accessible after tREC, if the oscillator is running and the oscillator countdown chain is not in reset (Register A). This time period allows the system to stabilize after power is applied. If the oscillator is not enabled, the oscillator enable bit is enabled on powerup, and the device becomes immediately accessible.
Time, Calendar, and Alarm Locations
The time and calendar information is obtained by reading the appropriate register bytes. The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents of the 12 time, calendar, and alarm bytes can be either binary or binary-coded decimal (BCD) format. Tables 3A and 3B show the BCD and binary formats of the 12 time, date, and alarm registers, control registers A to D, plus the two extended registers that reside in bank 1 only (bank 0 and bank 1 switching is explained later in this text). The day-of-week register increments at midnight, incrementing from 1 through 7. The day-of-week register is used by the daylight saving function, and so the value 1 is defined as Sunday. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to logic 1 to prevent updates from occurring while access is being attempted. In addition to writing the 12 time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of Register B must be set to the appropriate logic level. All 12 time, calendar, and alarm bytes must use the same data mode. The set bit in Register B should be cleared after the data mode bit has been written to allow the real time clock to update the time and calendar bytes. Once initialized, the real time clock makes all updates in the selected mode. The data mode cannot be changed without reinitializing the 12 data bytes. Tables 3A and 3B show the BCD and binary formats of the 12 time, calendar, and alarm locations. The 24-12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents PM when it is logic 1. The time, calendar, and alarm bytes are always accessible because they are double-buffered. Once per second, the eight bytes are advanced by one second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc., may not correlate. The probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later in this text.
Power Control
The power control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the device inhibits read and write access. If VPF is less than VBAT, the device power is switched from V CC to the higher of V BAT or V BAUX when VCC drops below VPF. If VPF is greater than the higher of VBAT or VBAUX, the device power is switched from VCC to the higher of VBAT or VBAUX when VCC drops below the higher backup source. The registers are maintained from the VBAT or VBAUX source until VCC is returned to nominal levels. After V CC returns above VPF, read and write access is allowed after tREC.
Table 2. Power Control
SUPPLY CONDITION VCC < VPF, VCC < (VBAT | VBAUX) VCC < VPF, VCC > (VBAT | VBAUX) VCC > VPF, VCC < (VBAT | VBAUX) VCC > VPF, VCC > (VBAT | VBAUX) READ/WRITE ACCESS No No Yes Yes POWERED BY VBAT or VBAUX VCC VCC VCC
12
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Real-Time Clocks
The alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day, if the alarm enable bit is high. In this mode, the "0" bits in the alarm registers and the corresponding time registers must always be written to 0 (see Table 3A and 3B). Writing the 0 bits in the alarm and/or time registers to 1 can result in undefined operation. The second use condition is to insert a "don't care" state in one or more of the alarm bytes. The don't care code is any hexadecimal value from C0 to FF. The two most significant bits of each byte set the don't care condition when at logic 1. An alarm will be generated each hour when the "don't care" bits are set in the hours byte. Similarly, an alarm is generated every minute with don't care codes in the hours and minute alarm bytes. An alarm is generated every second with don't care codes in the hours, minutes, and seconds alarm bytes. All 128 bytes can be directly written or read except for the following: 1) Registers C and D are read-only. 2) Bit 7 of register A is read-only. 3) The MSB of the seconds byte is read-only.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Table 3A. Time, Calendar, and Alarm Data Modes--BCD Mode (DM = 0)
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh Bank 1, 48h Bank 1, 49h UIP SET IRQF VRT PIE PF 0 10 Date BIT 7 0 0 0 0 AM/PM 0 AM/PM 0 0 0 0 0 0 0 0 0 10 Year DV2 DV1 AIE AF 0 DV0 UIE UF 0 RS3 SQWE 0 0 BIT 6 BIT 5 10 Seconds 10 Seconds 10 Minutes 10 Minutes 0 0 0 10 Date 0 10 Month 10 Hour 10 Hour 10 Hour 10 Hour 0 0 Date Month Year RS2 DM 0 0 Century Date RS1 24/12 0 0 RS0 DSE 0 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Alarm Day Date Month Year Control Control Control Control Century Date Alarm RANGE 00-59 00-59 00-59 00-59 1-12 +AM/PM 00-23 1-12 +AM/PM 00-23 01-07 01-31 01-12 00-99 -- -- -- -- 00-99 01-31 Seconds Seconds Minutes Minutes Hours Hours Day
10 Century
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds register, 0 bits in the time and date registers can be written to 1, but can be modified when the clock updates. 0 bits should always be written to 0 except for alarm mask bits.
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Table 3B. Time, Calendar, and Alarm Data Modes--Binary Mode (DM = 1)
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh Bank 1, 48h Bank 1, 49h BIT 7 0 0 0 0 AM/PM 0 AM/PM 0 0 0 0 0 UIP SET IRQF VRT DV2 PIE PF 0 10 Century 10 Date DV1 AIE AF 0 DV0 UIE UF 0 BIT 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Year RS3 SQWE 0 0 RS2 DM 0 0 Date RS1 24/12 0 0 Century RS0 DSE 0 0 0 0 0 0 Date Month BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Hours Hours Day Hours Hours Alarm Day Date Month Year Control Control Control Control Century Date Alarm RANGE 00-3B 00-3B 00-3B 00-3B 1-0C +AM/PM 00-17 1-0C +AM/PM 00-17 01-07 01-1F 01-0C 00-63 -- -- -- -- 00-63 01-1F Seconds Seconds Minutes Minutes
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds register, 0 bits in the time and date registers can be written to 1, but can be modified when the clock updates. 0 bits should always be written to 0 except for alarm mask bits.
Control Registers
The four control registers (A, B, C, and D) reside in
both bank 0 and bank 1. These registers are accessible at all times, even during the update cycle.
Register A (0Ah)
MSB
BIT 7 UIP BIT 6 DV2 BIT 5 DV1 BIT 4 DV0 BIT 3 RS3 BIT 2 RS2 BIT 1 RS1
LSB
BIT 0 RS0
Bit 7: Update In Progress (UIP). This bit is a status flag that can be monitored. When the UIP bit is 1, the update transfer will soon occur. When UIP is 0, the update transfer does not occur for at least 244s. The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read-only. Writing the SET bit in Register B to 1 inhibits any update transfer and clears the UIP status bit.
Bits 6, 5, and 4: DV2, DV1, and DV0. These bits are used to turn the oscillator on or off and to reset the countdown chain. A pattern of 01X is the only combination of bits that turns the oscillator on and allows the RTC to keep time. A pattern of 11X enables the oscillator but holds the countdown chain in reset. The next update occurs at 500ms after a pattern of 01X is written to DV0, DV1, and DV2. DV0 is used to select bank 0 or bank 1 as defined in Table 5. When DV0 is set to 0, bank 0 is selected. When DV0 is set to 1, bank 1 is selected.
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Real-Time Clocks
Bits 3 to 0: Rate Selector Bits (RS3 to RS0). These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. The tap selected can be used to generate an output square wave (SQW pin) and/or a periodic interrupt. The user can do one of the following: 1) Enable the interrupt with the PIE bit; 2) Enable the SQW output pin with the SQWE or E32k bits; 3) Enable both at the same time and the same rate; or 4) Enable neither. Table 4 lists the periodic interrupt rates and the squarewave frequencies that can be chosen with the RS bits.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Table 4. Periodic Interrupt Rate and Square-Wave Output Frequency
EXT REG B E32K 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X SELECT BITS REGISTER A RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X tPI PERIODIC INTERRUPT RATE None 3.90625ms 7.8125ms 122.070s 244.141s 488.281s 976.5625s 1.953125ms 3.90625ms 7.8125ms 15.625ms 31.25ms 62.5ms 125ms 250ms 500ms * SQW OUTPUT FREQUENCY None 256Hz 128Hz 8.192kHz 4.096kHz 2.048kHz 1.024kHz 512Hz 256Hz 128Hz 64Hz 32Hz 16Hz 8Hz 4Hz 2Hz 32.768kHz
*RS3 to RS0 determine periodic interrupt rates as listed for E32K = 0.
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Register B (0Bh)
MSB
BIT 7 SET BIT 6 PIE BIT 5 AIE BIT 4 UIE BIT 3 SQWE BIT 2 DM BIT 1 24/12 BIT 0 DSE
LSB
Bit 7: SET. When the SET bit is 0, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to 1, any update transfer is inhibited, and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be executed in a similar manner. SET is a read/write bit and is not affected by any internal functions of the DS17x85. Bit 6: Periodic Interrupt Enable (PIE). This bit is a read/write bit that allows the periodic interrupt flag (PF) bit in Register C to drive the IRQ pin low. When PIE is set to 1, periodic interrupts are generated by driving the IRQ pin low at a rate specified by the RS3-RS0 bits of Register A. A 0 in the PIE bit blocks the IRQ output from being driven by a periodic interrupt, but the PF bit is still set at the periodic rate. PIE is not modified by any internal DS17x85 functions. Bit 5: Alarm Interrupt Enable (AIE). This bit is a read/write bit that, when set to 1, permits the alarm flag (AF) bit in Register C to assert IRQ. An alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes, including a don't care alarm code of binary 11XXXXXX. When the AIE bit is set to 0, the AF bit does not initiate the IRQ signal. The internal functions of the DS17x285/87 do not affect the AIE bit. Bit 4: Update-Ended Interrupt Enable (UIE). This bit is a read/write bit that enables the update-end flag (UF) bit in Register C to assert IRQ. The SET bit going high clears the UIE bit.
Bit 3: Square-Wave Enable (SQWE). When this bit is set to 1 and E32k = 0, a square-wave signal at the frequency set by RS3-RS0 is driven out on the SQW pin. When the SQWE bit is set to 0 and E32k = 0, the SQW pin is held low. SQWE is a read/write bit. SQWE is set to 1 when VCC is powered up. Bit 2: Data Mode (DM). This bit indicates whether time and calendar information is in binary or BCD format. The program sets the DM bit to the appropriate format and can be read as required. This bit is not modified by internal functions. A 1 in DM signifies binary data, while a 0 in DM specifies binary-coded decimal (BCD) data. Bit 1: 24/12 Control (24/12). This bit establishes the format of the hours byte. A 1 indicates the 24-hour mode and a 0 indicates the 12-hour mode. This bit is read/write and is not affected by internal functions. Bit 0: Daylight Saving Enable (DSE). This bit is a read/write bit that enables two daylight saving adjustments when DSE is set to 1. On the first Sunday in April, the time increments from 1:59:59AM to 3:00:00AM. On the last Sunday in October when the time first reaches 1:59:59AM, it changes to 1:00:00AM. When DSE is enabled, the internal logic tests for the first/last Sunday condition at midnight. If the DSE bit is not set when the test occurs, the daylight saving function does not operate correctly. These adjustments do not occur when the DSE bit is zero. This bit is not affected by internal functions.
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Register C (0Ch)
MSB
BIT 7 IRQF BIT 6 PF BIT 5 AF BIT 4 UF BIT 3 0 BIT 2 0 BIT 1 0
LSB
BIT 0 0
Bit 7: Interrupt Request Flag (IRQF). This bit is set to 1 when any of the following are true: PF = PIE = 1 WF = WIE = 1 AF = AIE = 1 KF = KSE = 1 UF = UIE = 1 RF = RIE = 1 Any time the IRQF bit is 1, the IRQ pin is driven low. Flag bits PF, AF, and UF are cleared after reading Register C. Bit 6: Periodic Interrupt Flag (PF). This is a read-only bit that is set to 1 when an edge is detected on the selected tap of the divider chain. The RS3-RS0 bits establish the periodic rate. PF is set to 1 independent
of the state of the PIE bit. When both PF and PIE are 1s, the IRQ signal is active and sets the IRQF bit. Reading Register C clears this bit. Bit 5: Alarm Interrupt Flag (AF). A 1 in this bit indicates that the current time has matched the alarm time. If the AIE bit is also 1, the IRQ pin goes low and a 1 appears in the IRQF bit. Reading Register C clears this bit. Bit 4: Update-Ended Interrupt Flag (UF). This bit is set after each update cycle. When the UIE bit is set to 1, the 1 in UF causes the IRQF bit to be 1, which asserts IRQ. Reading Register C clears this bit. Bits 3 to 0: Unused. These unused bits always read 0 and cannot be written.
Register D (0Dh)
MSB
BIT 7 VRT BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0
LSB
BIT 0 0
Register D (0Dh)
Bit 7: Valid RAM and Time (VRT). This bit indicates the condition of the battery connected to the VBAT and VBAUX pin. If either supply is above the internal voltage threshold, VRTTRIP, the bit will be high. This bit is not writeable and should always be a 1 when read. If a 0 is
ever present, an exhausted internal lithium energy source is indicated and both the contents of the RTC data and RAM data are questionable. Bits 6 to 0: Unused. These bits cannot be written and, when read, always read 0.
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Nonvolatile RAM
The user RAM bytes are not dedicated to any special function within the DS17x85. They can be used by the processor program as battery-backed memory and are fully available during the update cycle. The user RAM is divided into two separate memory banks. When the bank 0 is selected, the 14 real-time clock registers and 114 bytes of user RAM are accessible. When bank 1 is selected, an additional 2kbytes, 4kbytes, or 8kbytes of user RAM are accessible through the extended RAM address and data registers. implemented on these bits so that set bits remain stable throughout the read cycle. All bits that were set are cleared when read and new interrupts that are pending during the read cycle are held until after the cycle is completed. One, two, or three bits can be set when reading Register C. Each used flag bit should be examined when read to ensure that no interrupts are lost. The flag bits in Extended Register 4A are not automatically cleared following a read. Instead, each flag bit can be cleared to 0 only by writing 0 to that bit. When using the flag bits with fully enabled interrupts, the IRQ line is driven low when an interrupt flag bit is set and its corresponding enable bit is also set. IRQ is held low as long as at least one of the six possible interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is 1 whenever the IRQ pin is being driven low as a result of one of the six possible active sources. Therefore, determination that the DS17x85/DS17x87 initiated an interrupt is accomplished by reading Register C and finding IRQF = 1. IRQF remains set until all enabled interrupt flag bits are cleared to 0.
Interrupts
The RTC includes six separate, fully automatic sources of interrupt for a processor: 1) Alarm Interrupt 2) Periodic Interrupt 3) Update-Ended Interrupt 4) Wake-Up Interrupt 5) Kickstart Interrupt 6) RAM Clear Interrupt The conditions that generate each of these independent interrupt conditions are described in detail in other sections of this data sheet. This section describes the overall control of the interrupts. The application software can select which interrupts, if any, are to be used. There are 6 bits, including 3 bits in Register B and 3 bits in Extended Register 4B, that enable the interrupts. The extended register locations are described later. Writing logic 1 to an interruptenable bit permits that interrupt to be initiated when the event occurs. A logic 0 in the interrupt-enable bit prohibits the IRQ pin from being asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is immediately set at an active level, although the event initiating the interrupt condition might have occurred much earlier. Therefore, there are cases where the software should clear these earlier generated interrupts before first enabling new interrupts. When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C or in Extended Register 4A. These flag bits are set regardless of the setting of the corresponding enable bit located either in Register B or in Extended Register 4B. The flag bits can be used in a polling mode without enabling the corresponding enable bits. However, care should be taken when using the flag bits of Register C as they are automatically cleared to 0 immediately after they are read. Double latching is
18
Oscillator Control Bits
A pattern of 01X in bits 4 to 6 of Register A turns the oscillator on and enables the countdown chain. A pattern of 11X (DV2 = 1, DV1 = 1, DV0 = X) turns the oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4 to 6 keep the oscillator off. When the DS17x87 is shipped from the factory, the internal oscillator is turned off. This feature prevents the lithium energy cell from being used until it is installed in a system.
Square-Wave Output Selection
Thirteen of the 15 divider taps are made available to a 1-of-16 multiplexer, as shown in Figure 1. The square wave and periodic interrupt generators share the output of the multiplexer. The RS0-RS3 bits in Register A establish the output frequency of the multiplexer. These frequencies are listed in Table 4. Once the frequency is selected, the output of the SQW pin can be turned on and off under program control with the square-wave enable bit (SQWE). If E32K = 0, the square-wave output is determined by the RS3 to RS0 bits. If E32K = 1, a 32kHz square wave is output on the SQW pin, regardless of the RS3 to RS0 bits' state. If E32K = ABE = 1 and a valid voltage is applied to VBAUX, a 32kHz square wave is output on SQW when VCC is below VTP.
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Real-Time Clocks
Periodic Interrupt Selection
The periodic interrupt causes the IRQ pin to go to an active state from once every 500ms to once every 122s. This function is separate from the alarm interrupt, which can be output from once per second to once per day. The periodic interrupt rate is selected using the same Register A bits that select the squarewave frequency (see Table 4). Changing the Register A bits affects both the square-wave frequency and the periodic interrupt output. However, each function has a separate enable bit in Register B. The SQWE and E32k bits control the square-wave output. Similarly, the periodic interrupt is enabled by the PIE bit in Register B. The periodic interrupt can be used with software counters to measure inputs, create output intervals, or await the next needed software function. an alarm if a match or if a don't care code is present in all alarm locations. There are three methods that can handle access of the RTC that avoid any possibility of accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If enabled, an interrupt occurs after every update cycle that indicates that over 999ms are available to read valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared before leaving the interrupt routine. A second method uses the update-in-progress (UIP) bit in Register A to determine if the update cycle is in progress. The UIP bit pulses once per second. After the UIP bit goes high, the update transfer occurs 244s later. If a low is read on the UIP bit, the user has at least 244s before the time/calendar data is changed. Therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244s. The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in Register A is set high between the setting of the PF bit in Register C (see Figure 4). Periodic interrupts that occur at a rate of greater than tBUC allow valid time and date information to be reached at each occurrence of the periodic interrupt. The reads should be complete within 1 (tPI/2 + tBUC) to ensure that data is not read during the update cycle.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Update Cycle
The DS17x85 executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to 1, the user copy of the double-buffered time, calendar, and alarm bytes is frozen and does not update as the time increments. However, the time countdown chain continues to update the internal copy of the buffer. This feature allows time to maintain accuracy independent of reading or writing the time, calendar, and alarm buffers, and also guarantees that time and calendar information is consistent. The update cycle also compares each alarm byte with the corresponding time byte and issues
1 SECOND UIP tBUC UF
tPI/2
PF t PI
tPI/2
tBUC = DELAY TIME BEFORE UPDATE CYCLE = 244s.
Figure 4. UIP and Periodic Interrupt Timing
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Extended Functions
The extended functions provided by the DS17x85/ DS17x87 that are new to the RAMified RTC family are accessed by a software-controlled bank-switching scheme, as illustrated in Table 5. In bank 0, the clock/calendar registers and 50 bytes of user RAM are in the same locations as for the DS1287. As a result, existing routines implemented within BIOS, DOS, or application software packages can gain access to the DS17x85/DS17x87 clock registers with no changes. Also in bank 0, an extra 64 bytes of RAM are provided at addresses just above the original locations for a total of 114 directly addressable bytes of user RAM. When bank 1 is selected, the clock/calendar registers and the original 50 bytes of user RAM still appear as bank 0. However, the extended registers that provide control and status for the extended functions are accessed in place of the additional 64 bytes of user RAM. The major extended functions controlled by the extended registers are listed below: * 64-Bit Silicon Serial Number * Century Counter * RTC Write Counter * Date Alarm * Auxiliary Battery Control/Status * Wake-Up * Kickstart * RAM Clear Control/Status * Extended RAM Access The bank selection is controlled by the state of the DV0 bit in register A. To access bank 0 the DV0 bit should be written to a 0. To access bank 1, DV0 should be written to 1. Register locations designated as reserved in the bank 1 map are reserved for future use by Dallas Semiconductor. Bits in these locations cannot be written and return a 0 if read.
Silicon Serial Number
A unique 64-bit lasered serial number is located in bank 1, registers 40h-47h. This serial number is divided into three parts. The first byte in register 40h contains a model number to identify the device type of the DS17x85/DS17x87. Registers 41h-46h contain a unique binary number. Register 47h contains a CRC byte used to validate the data in registers 40h-46h. The CRC polynomial is X8 + X5 + X4 + 1. See Figure 5. All 8 bytes of the serial number are read-only registers. The DS17x85/DS17x87 is manufactured such that no two devices contain an identical number in locations 41h-47h.
DEVICE DS17285/87 DS17485/87 DS17885/87 MODEL NUMBER 72h 74h 78h
POLYNOMIAL = X8 + X5 + X4 + 1
1ST STAGE X0
2ND STAGE X1
3RD STAGE X2
4TH STAGE X3 X4
5TH STAGE X5
6TH STAGE X6
7TH STAGE X7 INPUT DATA
8TH STAGE X8
Figure 5. CRC Polynomial
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Real-Time Clocks
Table 5. Extended Bank Register Bank Definition
Bank 0 DV0 = 0 00h Timekeeping and Control 0Dh 0Eh 50 Bytes - User RAM 3Fh 40h 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 7Fh 0Dh 0Eh 50 Bytes - User RAM Model Number Byte 1st Byte Serial Number 2nd Byte Serial Number 3rd Byte Serial Number 4th Byte Serial Number 5th Byte Serial Number 6th Byte Serial Number CRC Byte Century Byte Date Alarm Extended Control Register 4A Extended Control Register 4B Reserved Reserved RTC Address - 2 RTC Address - 3 Extended RAM Address LSB Extended RAM Address MSB Reserved Extended RAM Data Port Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTC Write Counter Reserved 7Fh 00h Timekeeping and Control Bank 1 DV0 = 1
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
64 Bytes - User RAM
Note: Reserved bits can be written to any value, but always read back as zeros.
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Century Counter
A register has been added in bank 1, location 48H, to keep track of centuries. The value is read in either binary or BCD according to the setting of the DM bit. As a result, system power can be applied upon such events as a key closure or modem ring-detect signal. To use either the wake-up or the kickstart functions, the DS17x85/DS17x87 must have an auxiliary battery connected to the VBAUX pin, the oscillator must be running, and the countdown chain must not be in reset (Register A DV2, DV1, DV0 = 01X). If DV2 and DV1 are not in this required state, the PWR pin is not driven low in response to a kickstart or wake-up condition while in battery-backed mode. The wake-up feature is controlled through the wake-up interrupt-enable bit in Extended Control Register 4B (WIE, bank 1, 04BH). Setting WIE to 1 enables the wake-up feature, clearing WIE to 0 disables it. Similarly, the kickstart interrupt-enable bit in Extended Control Register 4B (KSE, bank 1, 04BH) controls the kickstart feature. A wake-up sequence occurs as follows: When wake-up is enabled through WIE = 1 while the system is powered down (no VCC voltage), the clock/calendar monitors the current date for a match condition with the date alarm register (bank 1, register 049H). With the date alarm register, the hours, minutes, and seconds alarm bytes in the clock/calendar register map (bank 0, registers 05H, 03H, and 01H) are also monitored. As a result, a wake-up occurs at the date and time specified by the date, hours, minutes, and seconds alarm register values. This additional alarm occurs regardless of the programming of the AIE bit (bank 0, register B, 0BH). When the match condition occurs, the PWR pin is automatically driven low. This output can be used to turn on the main system power supply that provides VCC voltage to the DS17x85/DS17x87 as well as the other major components in the system. Also at this time, the wake-up flag (WF, bank 1, register 04AH) is set, indicating that a wake-up condition has occurred. A kickstart sequence occurs when kickstarting is enabled through KSE = 1. While the system is powered down, the KS input pin is monitored for a low-going transition of minimum pulse width tKSPW. When such a transition is detected, the PWR line is pulled low, as it is for a wake-up condition. Also at this time, the kickstart flag (KF, bank 1, register 04AH) is set, indicating that a kickstart condition has occurred.
RTC Write Counter
An 8-bit counter located in extended register bank 1, 5Eh, counts the number of times the RTC is written to. This counter is incremented on the rising edge of the WR signal every time that the CS signal qualifies it. This counter is a read-only register and rolls over after 256 RTC write pulses. This counter can be used to determine if and how many RTC writes have occurred since the last time this register was read.
Auxiliary Battery
The VBAUX input is provided to supply power from an auxiliary battery for the DS17x85/DS17x87 kickstart, wake-up, and SQW output in the absence of VCC functions. This power source must be available to use these auxiliary functions when no VCC is applied to the device. The auxiliary battery enable (ABE; bank 1, register 04BH) bit in Extended Control Register 4B is used to turn the auxiliary battery on and off for the above functions in the absence of VCC. When set to 1, VBAUX battery power is enabled; when cleared to 0, V BAUX battery power is disabled to these functions. In the DS17x85/DS17x87, this auxiliary battery can be used as the primary backup power source for maintaining the clock/calendar, user RAM, and extended external RAM functions. This occurs if the VBAT pin is at a lower voltage than V BAUX . If the DS17x85 is to be backed up using a single battery with any auxiliary functions enabled, then VBAUX should be used and VBAT should be grounded. If VBAUX is not to be used, it should be grounded and ABE should be cleared to 0.
Wake-Up/Kickstart
The DS17x85/DS17x87 incorporates a wake-up feature that powers on the system at a predetermined date and time through activation of the PWR output pin. In addition, the kickstart feature allows the system to be powered up in response to a low-going transition on the KS pin, without operating voltage applied to the VCC pin.
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Real-Time Clocks
The timing associated with both the wake-up and kickstarting sequences is illustrated in the WakeUp/Kickstart Timing Diagram (Figure 6). The timing associated with these functions is divided into five intervals, labeled 1 to 5 on the diagram. The occurrence of either a kickstart or wake-up condition causes the PWR pin to be driven low, as described above. During interval 1, if the supply voltage on the DS17x85/DS17x87 VCC pin rises above the greater of VBAT or VPF before the power-on timeout period (tPOTO) expires, then PWR remains at the active-low level. If VCC does not rise above the greater of VBAT or VPF in this time, then the PWR output pin is turned off and returns to its high-impedance level. In this event, the IRQ pin also
VBAT VPF *CONDITION VPF < VBAT 0V VPF VBAT *CONDITION VBAT > VPF 0V tPOTP WF/KF (INTERNAL)
remains tri-stated. The interrupt flag bit (either WF or KF) associated with the attempted power-on sequence remains set until cleared by software during a subsequent system power-on. If VCC is applied within the timeout period, then the system power-on sequence continue as shown in intervals 2 to 5 in the timing diagram. During interval 2, PWR remains active and IRQ is driven to its active-low level, indicating that either WF or KF was set in initiating the power-on. In the diagram KS is assumed to be pulled up to the VBAUX supply. Also at this time, the PAB bit is automatically cleared to 0 in response to a successful power-on. The PWR line remains active as long as the PAB remains cleared to 0.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
VIH KS VIL VIH PWR HIGH-IMPEDANCE VIL VIH IRQ HIGH-IMPEDANCE VIL
tKSPW
1
2
3
4
5
*THIS CONDITION CAN OCCUR WITH THE 3V DEVICE. NOTE: THE TIME INTERVALS SHOWN ABOVE ARE REFERENCED IN THE WAKE-UP/KICKSTART SECTION.
Figure 6. Wake-Up/Kickstart Timing Diagram
Table 6. Wake-Up/Kickstart Timing
(TA =+25C)
PARAMETER Kickstart-Input Pulse Width Wake-Up/Kickstart Power-On Timeout SYMBOL tKSPW tPOTO CONDITIONS MIN 2 2 TYP MAX UNITS s s
Note: Wake-up/kickstart timeout is generated only when the oscillator is enabled and the countdown chain is not reset. ____________________________________________________________________ 23
Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
At the beginning of interval 3, the system processor has begun code execution and clears the interrupt condition of WF and/or KF by writing zeros to both of these control bits. As long as no other interrupt within the DS17x85/DS17x87 is pending, the IRQ line is taken inactive once these bits are reset. Execution of the application software can proceed. During this time, the wake-up and kickstart functions can be used to generate status and interrupts. WF is set in response to a date, hours, minutes, and seconds match condition. KF is set in response to a low-going transition on KS. If the associated interrupt-enable bit is set (WIE and/or KSE), the IRQ line is driven active low in response to enabled event. In addition, the other possible interrupt sources within the DS17885/DS17887 can cause IRQ to be driven low. While system power is applied, the on-chip logic always attempts to drive the PWR pin active in response to the enabled kickstart or wake-up condition. This is true even if PWR was previously inactive as the result of power being applied by some means other than wake-up or kickstart. The system can be powered down under software control by setting the PAB bit to logic 1. This causes the open-drain PWR pin to be placed in a high-impedance state, as shown at the beginning of interval 4 in the timing diagram. As VCC voltage decays, the IRQ output pin is placed in a high-impedance state when V CC goes below VPF. If the system is to be again powered on in response to a wake-up or kickstart, then the WF and KF flags should be cleared, and WIE and/or KSE should be enabled prior to setting the PAB bit. During interval 5, the system is fully powered down. Battery backup of the clock calendar and NV RAM is in effect and IRQ is tri-stated, and monitoring of wake-up and kickstart takes place. If PRS = 1, PWR stays active; otherwise, if PRS = 0, PWR is high impedance. completed. If VCC is present at the time of the RAM clear and RIE = 1, the IRQ line is also driven low upon completion. Writing a zero to the RF bit clears the interrupt condition. The IRQ line then returns to its inactive high level, provided there are no other pending interrupts. Once the RCLR pin is activated, all read/write accesses are locked out for a minimum recover time, specified as tREC in Electrical Characteristics. When RCE is cleared to 0, the RAM clear function is disabled. The state of the RCLR pin has no effect on the contents of the user RAM, and transitions on the RCLR pin have no effect on RF.
Extended RAM
The DS17x85/DS17x87 provide 2k, 4k, or 8k x 8 of onchip SRAM that is controlled as nonvolatile storage sustained from a lithium battery. On power-up, the RAM is taken out of write-protect status by the internal powerOK signal (POK) generated from the write-protect circuitry. The on-chip SRAM is accessed through the eight multiplexed address/data lines AD7 to AD0. Three on-chip latch registers control access to the SRAM. Two registers are used to hold the SRAM address, and the other register is used to hold read/write data. Access to the extended RAM is controlled by three of the registers shown in Table 5. The extended registers in bank 1 must first be selected by setting the DV0 bit in register A to logic 1. The address of the RAM location to be accessed must be loaded into the extended RAM address registers located at 50h and 51h. The least significant address byte should be written to location 50h, and the most significant bits (right-justified) should be loaded in location 51h. Data in the addressed location can be read by performing a read operation from location 53h, or written to by performing a write operation to location 53h. Data in any addressed location can be read or written repeatedly without changing the address in location 50h and 51h. To read or write consecutive extended RAM locations, a burst mode feature can be enabled to increment the extended RAM address. To enable the burst mode feature, set the BME bit in the Extended Control Register 4Ah to logic 1. With burst mode enabled, write the extended RAM starting address location to registers 50h and 51h. Then read or write the extended RAM data from/to register 53h. The extended RAM address locations are automatically incremented on the rising edge of RD or WR only when register 53h is being accessed. See the Burst Mode Timing Waveform.
RAM Clear
The DS17x85/DS17x87 provide a RAM clear function for the 114 bytes of user RAM. When enabled, this function can be performed regardless of the condition of the VCC pin. The RAM clear function is enabled or disabled through the RAM clear-enable bit (RCE; bank 1, register 04BH). When this bit is set to logic 1, the 114 bytes of user RAM is cleared (all bits set to 1) when an active-low transition is sensed on the RCLR pin. This action has no effect on either the clock/calendar settings or the contents of the extended RAM. The RAM clear flag (RF, bank 1, register 04AH) is set when the RAM clear operation has been
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
AS
CS
AD0-7
53H
DATA PWRWL PWRWH
DATA
DS OR R/W
ADDRESS + 1
ADDRESS + 2
Figure 7. Burst Mode Timing Waveform
Extended Control Registers
Two extended control registers are provided to supply control and status information for the extended functions offered by the DS17x85/DS17x87. These are des-
ignated as Extended Control Registers 4A and 4B, and are located in register bank 1, locations 04AH and 04BH, respectively. The functions of the bits within these registers are described as follows.
Extended Control Register (4Ah)
MSB
BIT 7 VRT2 BIT 6 INCR BIT 5 BME BIT 4 * BIT 3 PAB BIT 2 RF BIT 1 WF
LSB
BIT 0 KF
*Reserved bit. This bit is reserved for future use. It can be read and written, but has no effect on operation.
Bit 7: Valid RAM and Time 2 (VRT2). This status bit gives the condition of the auxiliary battery. It is set to logic 1 condition when the external lithium battery is connected to the VBAUX. If this bit is read as logic 0, the external battery should be replaced. Bit 6: Increment in Progress Status (INCR). This bit is set to 1 when an increment to the time/date registers is in progress and the alarm checks are being made. INCR is set to 1 at 122s before the update cycle starts and is cleared to 0 at the end of each update cycle. Bit 5: Burst Mode Enable (BME). The burst mode enable bit allows the extended user RAM address registers to automatically increment for consecutive reads and writes. When BME is set to logic 1, the automatic incrementing is enabled and when BME is set to a logic 0, the automatic incrementing is disabled.
Bit 3: Power Active-Bar Control (PAB). When this bit is 0, the PWR pin is in the active low state. When this bit is 1, the PWR pin is in the high-impedance state. The user can write this bit to logic 1 or 0. If either WF and WIE = 1 or KF and KSE = 1, the PAB bit is cleared to 0. Bit 2: RAM Clear Flag (RF). This bit is set to logic 1 when a high-to-low transition occurs on the RCLR input if RCE = 1. Writing this bit to logic 0 clears it. This bit can also be written to logic 1 to force an interrupt condition. Bit 1: Wake-Up Alarm Flag (WF). This bit is set to 1 when a wake-up alarm condition occurs or when the user writes it to 1. WF is cleared by writing it to 0. Bit 0: Kickstart Flag (KF). This bit is set to 1 when a kickstart condition occurs or when the user writes it to 1. This bit is cleared by writing it to logic 0.
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Extended Control Register (4Bh)
MSB
BIT 7 ABE BIT 6 E32k BIT 5 CS BIT 4 RCE BIT 3 PRS BIT 2 RIE BIT 1 WIE
LSB
BIT 0 KSE
Bit 7: Auxiliary Battery Enable (ABE). When written to logic 1, this bit enables the V BAUX pin for extended functions. Bit 6: Enable 32.768kHz Output (E32k). When written to logic 1, this bit enables the 32.768kHz oscillator frequency to be output on the SQW pin. E32k is set to 1 when VCC is powered up. Bit 5: Crystal Select (CS). When CS is set to 0, the oscillator is configured for operation with a crystal that has a 6pF specified load capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal. CS is disabled in the DS17x87 module and should be set to CS = 0. Bit 4: RAM Clear Enable (RCE). When set to 1, this bit enables a low level on RCLR to clear all 114 bytes of user RAM. When RCE = 0, RCLR and the RAM clear function are disabled. Bit 3: PAB Reset Select (PRS). When set to 0, the PWR pin is set high impedance when the DS17x85 goes into power fail. When set to 1, the PWR pin remains active upon entering power fail.
Bit 2: RAM Clear Interrupt Enable (RIE). When RIE is set to 1, the IRQ pin is driven low when a RAM clear function is completed. Bit 1: Wake-Up Alarm Interrupt Enable (WIE). When VCC voltage is absent and WIE is set to 1, the PWR pin is driven active low when a wake-up condition occurs, causing the WF bit to be set to 1. When VCC is then applied, the IRQ pin is also driven low. If WIE is set while system power is applied, both IRQ and PWR are driven low in response to WF being set to 1. When WIE is cleared to 0, the WF bit has no effect on the PWR or IRQ pins. Bit 0: Kickstart Interrupt Enable (KSE). When VCC voltage is absent and KSE is set to 1, the PWR pin is driven active low when a kickstart condition occurs (KS pulsed low), causing the KF bit to be set to 1. When VCC is then applied, the IRQ pin is also driven low. If KSE is set to 1 while system power is applied, both IRQ and PWR are driven low in response to KF being set to 1. When KSE is cleared to 0, the KF bit has no effect on the PWR or IRQ pins.
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Real-Time Clocks
System Maintenance Interrupt (SMI) Recovery Stack
An SMI recovery register stack is located in the extended register bank, locations 4Eh and 4Fh. This register stack, shown below, can be used by the BIOS to recover from an SMI occurring during an RTC read or write. The RTC address is latched on the falling edge of the ALE signal. Each time an RTC address is latched, the register address stack is pushed. The stack is only four registers deep, holding the three previous RTC addresses in addition to the current RTC address being accessed. Figure 8 illustrates how the BIOS could recover the RTC address when an SMI occurs. 1) The RTC address is latched. 2) An SMI is generated before an RTC read or write occurs. 3 RTC address 0Ah is latched and the address from 1 is pushed to the "RTC Address-1" stack location. This step is necessary to change the bank select bit, DV0 = 1. 4) RTC address 4Eh is latched and the address from 1 is pushed to location 4Eh, "RTC Address-2" while 0Ah is pushed to the "RTC Address-1" location. The data in this register, 4Eh, is the RTC address lost due to the SMI.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
RTC ADDRESS RTC ADDRESS-1 4Eh RTC ADDRESS-2 4Fh RTC ADDRESS-3 SMI Recovery Stack
7 DV0
6 AD6
5 AD5
4 AD4
3 AD3
2 AD2
1 AD1
0 AD0
REGISTER BIT DEFINITION
ALE 1 2 3 4
Figure 8. ALE Waveform
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Pin Configurations
TOP VIEW
PWR 1 X1 2 X2 3 AD0 4 AD1 5 AD2 6 AD3 7 AD4 8 AD5 9 AD6 10 AD7 11 GND 12
24 VCC 23 SQW 22 VBAUX 21 RCLR 20 VBAT
PWR 1 N.C. 2 N.C. 3 AD0 4 AD1 5 AD2 6 AD3 7 AD4 8 AD5 9 AD6 10 AD7 11 GND 12
24 VCC 23 SQW 22 VBAUX 21 RCLR 20 N.C.
DS17285 DS17485 DS17885
19 IRQ 18 KS 17 RD 16 GND 15 WR 14 ALE 13 CS
DS17287 DS17487 DS17887
19 IRQ 18 KS 17 RD 16 N.C. 15 WR 14 ALE 13 CS
SO, PDIP
EDIP
IRQ VBAT RCLR VBAUX SQW VCC VCC PWR X1 X2 N.C. AD0 AD1 AD2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24
KS RD GND WR ALE CS GND GND AD7 AD6 N.C. AD5 AD4 AD3
DS17285 DS17485 DS17885
23 22 21 20 19 18 17 16 15
TSOP
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Ordering Information
PART DS17285-3 DS17285-5 DS17285E-3 DS17285E-3+ DS17285E-5 DS17285E-5+ DS17285EN-3 DS17285N-5 DS17285S-3 TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C PINPACKAGE 24 PDIP 24 PDIP 28 TSOP 28 TSOP 28 TSOP 28 TSOP 24 SO (300 mils) 24 SO (300 mils) 24 SO (300 mils) 24 SO (300 mils) 24 SO (300 mils) TOP MARK* DS17285-3 DS17285-5 DS17285E3 DS17285E3 DS17285E5 DS17285E5 DS17285E3 DS17285N5 DS17285S-3 DS17285SN3 DS17285S-5 DS17285SN3 DS17285SN5 DS17885S-5 DS17287-3 DS17287-5 DS17485-3 DS17485-5 DS17485E3 DS17485E3 DS17485E5 DS17485E5 DS17485S-3 DS17485S-5 DS17887-5 DS17887-5IND 0C to +70C 24 EDIP DS17887-3IND -40C to +85C 24 EDIP DS17887-3 0C to +70C DS17885SN-5 -40C to +85C 0C to +70C DS17487-5 DS17487-5IND DS17885-3 DS17885-5 DS17885E-3 DS17885E-3+ DS17885E-5 DS17885E-5+ DS17885S-3 0C to +70C 24 EDIP DS17487-3IND -40C to +85C 24 EDIP DS17487-3 0C to +70C PART DS17485SN-5 TEMP RANGE -40C to +85C PINPACKAGE 24 SO (300 mils) 24 EDIP TOP MARK* DS17485SN5 DS17487-3 DS17487-3 REAL TIME IND DS17487-5 DS17487-5 REAL TIME IND DS17885-3 DS17885-5 DS17885E3 DS17885E3 DS17885E5 DS17885E5 DS17885S-3 DS17885S-5 DS17885SN5 DS17887-3 DS17887-3 REAL TIME IND DS17887-5 DS17887-5 REAL TIME IND
-40C to +85C 28 TSOP -40C to +85C 0C to +70C
-40C to +85C 24 EDIP 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 24 PDIP 24 PDIP 28 TSOP 28 TSOP 28 TSOP 28 TSOP 24 SO (300 mils) 24 SO (300 mils) 24 SO (300 mils) 24 EDIP
DS17285S-3NT -40C to +85C DS17285S-5 DS17285SN-3 DS17285SN-5 DS17287-3 DS17287-5 DS17485-3 DS17485-5 DS17485E-3 DS17485E-3+ DS17485E-5 DS17485E-5+ DS17485S-3 DS17485S-5 0C to +70C -40C to +85C
24 SO -40C to +85C (300 mils) 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 24 EDIP 24 EDIP 24 PDIP 24 PDIP 28 TSOP 28 TSOP 28 TSOP 28 TSOP 24 SO (300 mils) 24 SO (300 mils)
-40C to +85C 24 EDIP
+ Denotes lead-free package. *A "+" anywhere on the top mark denotes a lead-free package. An "N" or "IND" denotes an industrial temperature range package. Note: A "-5" suffix denotes a VCC = 5V10% device, and a "-3" suffix denotes a VCC = 3V10% device.
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Real-Time Clocks DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Typical Operating Circuit
VCC CRYSTAL VCC
Thermal Information
PACKAGE DIP SO THETA-JA (C/W) 75 105 THETA-JC (C/W) 30 22
X1 IRQ ALE WR RD DS83C520 CS AD0-AD7 VSB
X2
VCC
SQW
Chip Information
DS17285 DS17485 DS17885
RCLR KS
TRANSISTOR COUNT DS17285/7: 139,000 TRANSISTOR COUNT DS17485/7: 233,000 TRANSISTOR COUNT DS17885/7: 421,000 SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS
VBAUX SUPPLY CONTROL CIRCUIT VCC
PWR
GND
VBAT
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
PACKAGE 24-Pin DIP (600 mils) 24-Pin SO (300 mils) 24-Pin EDIP (720 mils) 28-Pin TSOP OUTLINE DOCUMENT NUMBER 56-G5000-003 56-G4009-001 56-G0001-001 56-G5003-000
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.

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